The cost (or cost per bit) of a memory design is highly dependent on the area of the memory array. Larger array areas lead to better area efficiency (a lower cost per bit), because of the easier routing of interconnections, and more shared components such as row decoders, column decoders, sense amplifiers and buffers.
For example, FIGS. 1A and 1B show two different designs for a memory module, offering the same memory capacity. In FIG. 1A, memory array 105 is shown, which is accessed using row decoder 110 and column decoder 115. (FIGS. 1A-FIG. 1B are simplified drawings of a memory module: a person skilled in the art will recognize that there can be significantly more elements and circuitry in a memory module than are shown in FIGS. 1A-1B.)
In contrast to FIG. 1A, FIG. 1B shows four smaller memory arrays, such as memory array 120. Each smaller memory array 120 has its own row decoder 125 and column decoder 130. As can be seen, the footprint of the memory module in FIG. 1A is smaller than the footprint of the memory module in FIG. 1B.
The size of a memory array is limited by many constraints. These constraints can include the read noise margin requirements, latency requirements, and others. In addition, both emerging non-volatile memory (NVM) and future dynamic random access memory (DRAM) design can impose additional constraints to the memory array design.
NVM designs can use vertically connected devices as cell selectors, such as single direction bipolar junction transistors (BJTs) or diode devices, and bi-direction devices. These designs can reduce the cell size of NVMs. But these designs also introduce larger sneak currents at wordlines and bitlines.
Increasing the size of DRAM memory arrays means that more bits can be packed into the same amount of space on a DRAM module. Increasing the size of DRAM memory arrays also permits lower operating voltages and lower costs per bit. But as the operating voltages drop, leakage currents, such as gate leakage current and sub-threshold leakage current, become significant.
The traditional solutions to the problems of NVM designs and DRAM scaling are to reduce the array size or increase the operating voltage. But increasing the array size increases the area required by the memory module, which increases the cost. And increasing the operating voltage increases the power consumed by the memory module. Both of these consequences are undesirable.
A need remains for a way to reduce the implications of sneak currents and leakage currents in memory design.